The present invention relates to the field of semiconductors, and, more particularly, to a device including a power component and a circuit formed in a semiconductor material, and to associated methods of making the device.
VIPower technology is known, for example, from the publication EP-A-0322041 which describes an integrated structure comprising a bipolar power transistor and a MOSFET transistor interconnected in an xe2x80x9cemitter switchingxe2x80x9d configuration. This structure, also shown in FIG. 1 of the attached drawings, is formed on a substrate 10 of semiconductor material, for example an N+ type mono-crystalline silicon. (It should be noted that in the drawing the concentrations of the N type and P type impurities are indicated, as is usual, by adding the sign xe2x88x92 or + to the letters N and P; the letters N and P without the addition of a xe2x88x92 or + sign denote concentrations having an intermediate value).
Two epitaxial layers 11 and 12, of the Nxe2x88x92 and N type respectively, are formed on the substrate 10. The layer 11, together with the substrate 10, contains the collector region of the bipolar transistor. A metal layer 28 applied on the bottom surface of the substrate provides the collector terminal C.
A Pxe2x88x92 region 13, formed between the epitaxial layers 11 and 12, and therefore xe2x80x9cburiedxe2x80x9d between them, provides the base region of the transistor. A P+ insulation and deep contact base region 15 extends from the front surface of the chip, in other words from the surface opposite the collector terminal C, to the edge of the base region 13, defining within it an insulated N region 16. A second buried region 14, of the N+ type, is formed on the Pxe2x88x92 region 13 in such a way as to form a junction with it, and provides the emitter region of the transistor.
Inside the insulated region 16 there extends a P region 25, formed by a surface part with a low concentration (Pxe2x88x92) and by a deep part with a high concentration (P+) of impurities, which constitutes the xe2x80x9cbodyxe2x80x9d region of the MOSFET transistor and contains the channel of the transistor. A region 26 which constitutes the xe2x80x9csourcexe2x80x9d region of the MOSFET transistor is formed inside the xe2x80x9cbodyxe2x80x9d region 25. A strip 22 of electrically conducting material, which lies above the channel and is insulated from the surface of the chip by a thin layer of dielectric, constitutes the xe2x80x9cgatexe2x80x9d electrode, which is also a terminal of the device, indicated by G.
Electrically conducting strips 4 and 5 for surface contact are formed on the source region 26 and on the insulation region 15 respectively, and constitute the source terminals S of the MOSFET transistor and the base terminal B of the bipolar transistor respectively. The drain region of the MOSFET transistor includes the part of the insulated N region 16 lying between the buried emitter region 14 and the body region 25. The region 14, in this example, is not connected to external electrodes; if necessary, however, a deep contact (sinker) N+ region, extending from the front surface of the chip to the N+ region 14, can easily be formed to connect the emitter to an external electrode or to other components integrated in the same chip.
It is often convenient to form a circuit for controlling the power device in the same chip. Such a circuit includes low-power components operating at low voltage and capable of processing and amplifying signals and of driving the power device. It is commonly formed inside a pocket having a type of conductivity which is the opposite of that of the substrate, and therefore, in this example, of the P type, insulated from the rest of the chip by a reverse-biased junction, according to the known art of junction insulation.
FIG. 2 schematically and sectionally shows the principal regions of an integrated structure of this type. The power device is identical to that shown in FIG. 1, and the control circuit, in this example, is contained in two N type regions 16xe2x80x2, separated from each other and from the rest of the substrate by P type regions 13xe2x80x2 and 15xe2x80x2. These P type regions 131 and 15xe2x80x2 are produced at the same time as the P type regions 13 and 15. A buried N+ type region 14xe2x80x2, produced at the same time as the region 14 of the power device, is formed on the bottom of each of the regions 16xe2x80x2, and may provide, for example, the collector region or the drain region of a bipolar transistor or of a MOSFET transistor respectively, not illustrated further, both formed in the corresponding insulated region 16xe2x80x2.
The electrical insulation between the power device and the control circuit is obtained, as is known, by reverse biasing the junction which the P type pocket, formed by the buried region 13xe2x80x2 and by the insulation regions 15xe2x80x2, forms with the substrate. In practice, in the example illustrated, in operation, the contacts 5xe2x80x2 are connected to a terminal at a low potential, indicated by the ground symbol in the figure, of a power source, and the terminal C is connected to a terminal at high potential, indicated by +Vcc in the figure, of the same source.
This type of insulation, although very effective in most of the present structures of integrated circuits, has not proved satisfactory in integrated power circuits made by the VIPower technology. This is because a structure of the type described above includes a large number of N type and P type regions which are biased differently. They form junctions between each other which, during the operation of the device, in which currents of 4-8 A and voltages of 1000-2000 V are present, may give rise to numerous parasitic components, for example, in SCR devices, NPN and PNP transistors and capacitive devices sensitive to variations of voltage. Depending on the type of application and specific structure, these parasitic components, possibly interacting with each other, may cause both horizontal and vertical leakage currents, thus greatly reducing the efficiency of the electrical insulation between the control circuit and the power device, as well as between the components of the control circuit itself, which are disposed in different insulated regions.
To overcome these problems, it would be necessary to forgo junction insulation in favor of a more effective insulation system, such as that which makes use of layers of dielectric material to separate the active semiconductor regions from each other. The known art, however, does not include dielectric insulation techniques compatible with the VIPower technology and capable of withstanding the high voltages which are present. In this respect it should be noted that the control circuits normally operate at voltages varying between ground potential and a relatively low positive potential, usually not exceeding 50 V. The potential of an insulated N region 16xe2x80x2 will therefore have a value not very different from that of ground, while the potential of the N substrate may be higher, even much higher, than 1000 V. Consequently there would be very high voltages between the opposite surfaces of the dielectric layer of the insulation structure. Accordingly, very large thicknesses of dielectric, which cannot be produced by the available technologies, would be required to withstand these voltages.
An object of the present invention is to provide a semiconductor device comprising a bipolar power transistor and a MOSFET transistor interconnected in an emitter switching configuration, including an insulation structure of the control circuit which substantially prevents parasitic effects and which withstands the high operating voltages of the device.
This and other objects are achieved by a semiconductor device comprising a semiconductor material predominantly having a first type of conductivity and a power component and a control circuit formed in the semiconductor material. The device further includes a buried region having a second type of conductivity, buried in the semiconductor material and at least one insulated region of semiconductor material, containing at least part of the control circuit, disposed between a front surface of the device and the buried region. The insulated region is at least partially delimited by an insulating dielectric material. The device includes electrical contacts for each of the buried region and the semiconductor material.
Additionally, the insulating dielectric material may comprise a bottom layer which extends over the buried region and/or a wall which surrounds the insulated region. Also, the electrical contact for the buried region may comprise an electrically conductive element which extends through a portion of the wall, and is in contact with the buried region. Furthermore, in one embodiment, at least part of the wall may extend to a bottom of the buried region to laterally delimit the buried region.
The electrical contact for the buried region preferably includes a surface contact electrode adjacent the front surface of the device and a connecting region having the second type of conductivity, and extending from the surface contact electrode to the buried region. Also, the insulated region preferably has the first type of conductivity.
A method of making a semiconductor device including a power component and a control circuit as set forth above, includes the steps of forming a buried region having a second type of conductivity in a semiconductor material and providing an insulating dielectric material to define at least one insulated region between a front surface of the device and the buried region, the insulated region containing at least part of the control circuit. Also, the step of providing an insulating dielectric material preferably includes the steps of implanting oxygen at predetermined portions of the semiconductor material and forming at least one layer of silicon dioxide buried in the semiconductor material by annealing the oxygen implanted portions.